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UM6522/A
Versatile Interface Adap ter( VIA)
Features
. Two Shit bi-directional I/O ports n Two 16-bit programmable timer/counters m Serial data port n Single +5V power supply m TTL compatible except Port A n CMOS compatible peripheral Port A lines m Expanded "handshake" capability allows positive control of data transfers between processor and peripheral devices n Latched input and output registers n 1 MHz and 2 MHz Operation
General Description
The UM6522/A Versatile Interface Adapter (VIA) is a very flexible l/O control device. In addition, this device contains a pair of very powerful 16.bit interval timers, a serlalto-parallel/parallel-to-serial shift register and input data latching on the peripheral ports. Expanded handshaking capability allows control of bi-directional data transfers between VIA's in multiple processor Systems. Control of peripheral devices is handled primarily through two Shit bi-directional ports. Esch line tan be programmed as either an input or- an output. Several peripheral l/O lines tan be controlled directly from the interval timers for generating programmable frequency Square waves or for counting externally generated Pulses. To facilitate control of the many powerful features of this Chip, an interrupt flag register, an interrupt enable register and a pair of function control registers are provided.
Pin Configuration
Block Diagram
"SS c
PA0 c PA1 c 2 3 39 38 37 36 35 34 33 2 8 E $ ;: 30 29 28 27 26 25 24 23 22 21 PA2 r 4 PA3 c 5 PA4 c 6 PA5 c 7 PA6 c 8 PA7 [z PB0 c PB1 c 9 `O 11 13 14 15 16 17 16 19 20
] CA1 ] CA2 -J RSO ] RSl ] RS2 ] RS3 ]RES 1 DO 1 D' 1
D2
I] D3 2 D4 7 D5 7
PB2 [ `12
PB3 [
PB4 c PB5 [
D6
7 07 7 $2 7 CS1 Jcs2
PB6 c
PB7 [I CB1 c
CB2 c "cc c
5-18
GD
UMC
"Comments
UM6522/A
+8.0 VOLTS 1 +4v to +7v GND-2.0V to 0.5V GND-0.5V to Vcc +0.5V -65c to +1 5o"c . . oOc to +70c . . . . . ...<...< 1 Watt .
Absolute Maximum Ratings"
Supply Voltage . . . . Operating Voltage Range . Input Voitage Applied I/O P i n V o l t a g e A p p l i e d Storage Temperature Range Operating Temperature Range Maximum Power Dissipation
.
Stresses above those listed under "Absolute Maximum Ratings" may Cause permanent darnage to the device. These are stress ratings only. Functional Operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics
(Vcc = 5.OV * 5%, TA = 0 - 70C unless otherwise noted)
25C. f = 1 MHz SO, RSl , RSZ, RS3, CSl, CS2, -PA7, CAl, CAZ, PBO-PB7)
Test Load
PIN-
PIN 1OOpF 1 zz 1 = OPEN COLLECTOR OUTPUT TEST LOAD
C= 13OpF MAX. FOR DO-D7 C = 30 pF MAX. FOR ALL OTHER OUTPUTS
Figure 2. Test Load (for all Dynamit Parameters)
5-19
UM6522/A
Read Timing Characteristics (Figure 3.)
Note: tr, tf = 10 to 30ns.
CHIP SELECTS, R E G I S T E R SELECTS. Rm PERIPHERAL DATA
DATA BUS
Figure 3. Read Timing Characteristics
Write Timing Characteristics (Figure 4.)
Symbol
TCY
Parameter Cycle Time $2 Pulse Width Address Set-Up Time Address Hold Time R/W Set-Up Time Rm Hold Time Data Bus Set- Up Time Data Bus Hold Time Peripheral Data Delay Time Peripheral Data Delay Time to CMOS Levels
UM6522 Min. 1 0.44 180 0 180 0 300 10 1.0 2.0 I ) Max. 50 25 I
lJMS22A. - - .--- --. Min. 0.50 0.22 90 0 90 0 Max. 50 ;!5 1 I I
Unit
PS
TC
TACW TCAW TWGW TCWW TDCW THW TCFW TCMOS
I
T
-
PS ns ns ns ns ns ns PS PS q
Note: tr, tf = 10 to 30ns.
E
150 10 -
1 .o 2.0
&Y CLOCK
CHIP SELECTS. REGISTER SELECTS.
DATA BUS
PERIPHERAL DATA
Figure 4. Weite Timing Characteristics
5-20
UiWSSZZ/A
Peripheral Interface Characteristics
TSR 1
TSRZ
Shlft-Out Delay Time - Time from r& Falling Edge to CB2, Data Out Shift-in Setup Time - Time from CB2 Data in to G2 R ising Edge External Shift Glock (CBl) Setup Time Relative to & Trailing Edge Pulse Width - PB6 Input Pulse Pulse Width - CB1 Input Glock Pulse Spacing - PB6 Input Pulse Pulse Spacing - CB1 Input Pulse CAl, CB1 Set-Up Prior to Transition to Arm Latch Peripheral Data Hold After CAl, CB1 Transition Set-Up Required on CAl, CBl, CA2 or CB2 Prior tc ' Trictqering Edge Shift Register Glock - Delay from $2 to CB1 Rising Edge to CB1 Falling Edge 300 100 2 x Tcy 2 xTCY
300 TCY -
I
I
"C II.3 ns ns
Lf
1"'
33 59 5i 5h
Tm3
TIPW TICW
TIPS
2xTCy 2 x Tcy TC +50 150 I
TICS
TAI
+---+++
ns [ 1 I 5h 5e 1 5i ns I I 1 ns 1
.
`-PDH
-
TPWI
l
T,,,I IC Ta"
_
I
TDPR TDPL
200 125
ns ns
5k 5k
Timing Waveforms
READ IRA OPERATION c
CA2 "DATA TAKEN"
Figure 5a. CA2 Timing for Read Handshake, Pulse Mode
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UM6522/A
Timing Waveforms (Continued)
-
READ IRA OPERATION CA2 "DATA TAKEN" CA1 "DATA
READY"
Figure 5b. CA2 Timing for Read Handshake, Handshake Mode
$2
ft
-TWHS -TRS~ -
WRITE ORA, ORB OPERATION
CA2, CB2 "DATA READY" PA, PB PERIPHERAL DATA
Figure 5c. CA2, CB2 Timing for Write Handshake, Pulse Mode
WRITE ORA, ORB OPERATION CA2, CB2 "DATA READY" PA, PB PERIPHERAL DATA
- TWHS-
ATRs~
CAl, CE1 "DATA TAKEN"
ACTIVE TRANSITION ~
/ ji-
Figure 5d. CA2, CB2 Timing for Write Handshake, Handshake Mode
PA, PB PERIPHERAL INPUT DATA CAl, CB1 INPUT LATCHING CONTROL TRANSITION
Figure 5e. Peripheral Data Input Latch Timing
5-22
UM6522/A
Timing Waveforms (Continued)
$2 CB2 SHIFT DATA (OUTPUT) CB1 SHIFT CLOCK (INPUT OR OUTPUT) /-- DELAY TIME MEASURED FROM THE FIRST 42 FALLING EDGE AFTER Cl31 FALLING EDGE.
Figure 5f. Timing for Shift Out with Internal or External Shift Clocking
$2 CB2 SH i FT DATA (INPUT) CB1 SHIFT CLOCK (INPUT OR OUTPUT1
I
I
w
I
I
TSR~
1
w
I
1
c
I
1
I
Y
-TSRB -
SETUP TIME MEASURED TO THE FIRST RISING EDGE AFTER CB1 RISING EDGE
Figure 5g. Timing for Shift In with Internal or External Shift Clocking
CB1 SHIFT CLOCK l NPUT TICW -{
c - - TICS c
Figure 5h. External Shift Clocking
PB6 PULSE COUNT INPUT
f N TIPW * e
-\
TIPS
c
Figure 5i. Pulse Count Input Timing
CA1 , CA2 CBl, CB2
I
t+
INTERRUPT GENERATING EDGE
Figure 5j. Setup Time to Trigger Edge
Figure 5k. Shift-in/out with Internal Glock Delay CD2 to CB1 Edge
GD
UMC
UMSSZZ/A
Pin Description
RES (Reset) The reset input clears all internal registers to logic "0" (except Tl and T2 latches and counters and the Shift Register). This places all peripheral interface lines in the input state, disables the timers, shift register, etc. and disables interrupting from the Chip. $2 (Input Glock) The input clock is the System $2 clock and is used to trigger all data transfers between the System processor and the UM6522lA. Rm (Read/Write) The direction of the data transfers between the UM6522/A and the System processor is controlled by the Rm Iine. If R/W is low, data will be transferred out of the processor into the selected UM6522/A register (write Operation). If Rm is high and the chip is selected, data will be transferred out of the UM6522/A (read Operation). DBO-DB7 (Data Bus) The eight bi-directional data bus lines are used to transfer data between the UM6522/A and the System processor. During read cycles, the contents of the selected UM6522/A RSO- RS3 (Register Selects) The four Register Select inputs permit the System processor to select one of the 16 internal registers of the UM6522/A, as shown in Figure 6. IRQ (Interrupt Request) The Interrupt Request output goes low whenever an internal interrupt flag is set and the corresponding interrupt enable bit is a logic "1". This output is "opendrain" to allow the interrupt request Signal to be wire-ORed with other equivalent Signals in the System. register are placed on the data bus lines and transferred into the processor. During write cycles, these lines are high-impedance inputs and data IS transferred from the processor into the selected register. When the UM6522/A is unselected, the data bus lines are highimpedance. CSl, CS2 (Chip Selects) The two chip select inputs are normally connected to processor address lines either directly or through decoding. The selected UM6522/A register will be accessed when CS1 is high and CS2 is low.
Register Number 0 1
RS Coding RS3 0 0
I
RS2 0 0
I
RSI 0 0
I
RSO 0 1
I
Register Desig. ORB/IRB
I
Description Write Output Register "B" Output Register "A"
I
Read Input Reaister " B " Input Register "A"
ORAIIRA
15
1
1
1
1
1 ORAIIRA
Same as Reg 1 Except No. "Handshake"
I
Figure 6. UM6522/A Internal Register Summary .
5-24
UMSSZZ/A
PAO-PA7 [Peripheral A Port) The Peripheral A port consists of 8 lines which tan be individually programmed to act as inputs or Outputs under control of a Data Direction Register. The polarity of output pins is controlled by an Output Register and input data may be latched into an internal register under control of the CA1 Iine. All of these modes of Operation arecontrolled by the System processor through the internal control registers. These lines represent one Standard TTL load in the input mode and will drive one Standard TTL load in the output mode. Figure 7 illustrates the output circuit. PBO-PB7 (Peripheral B Port) The Peripheral B port consists of eight bi-directional lines which are controlled by an output register and a data direction register in much the same manner as the PA Port. In addition, the PB7 output Signal tan be controlled by one of the interval timers while the second t,imer tan be programmed to count pulses on the PB6 pin. Peripheral B lines represent one Standard TTL load in the input mode and will drive one Standard TTL load in the output mode. In addition, they are capable of sourcing 1 .OmA at 1.5VDC in the output mode to allow the Outputs to directly drive Darlington transistor circuits Figure 8 is the circuit schemat rc. CBl, CB2 (Peripheral B Control Lines) The Peripheral B control lines act as interrupt inputs or as handshake Outputs. As with CA1 andCA2, each line controls an interrupt flag with a corresponding interrupt enable bit. In addition, these lines act asa serial port under control of the Shift Register These lines represent one Standard TTL load in the input mode and will drive one Standard TTL load in the output mode. Unlike PBO-PB7. CB1 and CB2 cannot drive Darlington transistor circuits.
INPUT/ OUTPUT CONTROL PAO-PA7 CA2 I/O CONTROL OUTPUT DATA PBO-PB7 GBl. CB2
CAl, CA2 (Periphere1 A Cmtrol Lines) The two Peripheral A control lines act as interrupt inputs or as handshake Outputs. Esch line controls an internal interrupt flag with a corresponding interrupt enable bit. In addition, CA1 controls the latching of data on Peripheral A port input lines. CA1 is a high impedance input only; while CA2 represents one Standard TTL load in the input mode. CA2 will drive one Standard TTL load in the output mode.
INPUT DATA
Figure 7. Peripheral A Port Output Circuit
Figure 8. Peripheral B Port Output Circuit
Functional Description
Port A and Port B Operation Esch B-bit peripheral port has a Data Direction Register (DDRA, DDRB) for specifying whether the peripheral pins are to act as inputs or Outputs. A "0" in a bit of the Data Direction Register Causes the corresponding peripheral pin to act as an input. A "1" Causes the pin to act as an output. When programmed as an output each peripheral pin is also controlled by a corresponding bit in the Output Register (ORA' ORB). A "1" in the Output Register Causes the output to go high, and a "0" Causes the output to go low. Data may be written into Output Register bits corresponding to pins which are programmed as inputs. In this case, however, the output Signal is unaffected. Reading a peripheral port Causes the contents of the Input Register (IRA, IRB) to be transferred onto the Data Bus. With input latching disabled, IRA will always reflect the levels on the PA Pins. With input latching enabled and the selected active transition on CA1 having occurred, IRA will contain the data present on the PA lines at the time of the transition. Once IRA is read, however, it will appear transparent, reflecting the current state of the PA lines until the next "latching" transition. The IRB register operates similar to the IRA register. However, for pins programmed as Outputs there is a difference. When reading IRA, the level on the pin determines whether a "0" or a "1" is sensed. When reading IRB, however, the bit stored in the output register, ORB, is the bit sensed. Thus, for Outputs which have large loading effects and which pull an output "1" down or which pull an output "0" up, reading IRA may result in reading a "0" when a "1" was actually programmed, and reading a "1" when a "0" was programmed. Reading I RB, on the other hand, will read the "1" or "0" level actually programmed, no matter what the loading on the pin. Figures 9, 10 and 11 illustrate the formats of the port registers. In addition, the input latching modes are selected by the Auxiliary Control Register (Figure 17.)
GD
UMC
UM6522/A
the processor, which then reads the data, causing generation of a "Data Taken" Signal. The peripheral device responds by making new data available. This process continues until the data transfer is complete. In the UM6522/A, automatic " R e a d " H a n d s h a k i n g i s possible on the Peripheral A port only. The CA1 interrupt input pin accepts the "Data Ready" Signal and CA2 generates the "Data Taken" Signal. The "Data Ready" Signal will set an internal flag which may interrupt the processor or which may be polled under program control. `The "Data Taken" Signal tan either be a pulse or a level which is set low by the System processor and is cleared by the "Data Ready" Signal. These Options are shown in Figure 12 which illustrates the normal Read Handshaking sequence. REG 1 -ORA/IRA
Handshake Control of Data Transfer The UM6522/A allows positive control of data transfer between the System processor and peripheral devices through the Operation of "handshake" lines. Port A lines (CAI, CA2) handshake data on both a read and a write Operation while the Port B lines (CBI, CB2) handshake on a write Operation only. Read Handshake Positive control of data transfer from peripheral devices into the System processor tan be accomplished very effectively using Read Handshaking. In this case, the peripheral device must generate the equivalent of a "Data Ready" Signal to the processor signifying that valid data is present on the peripheral Port. This Signal normally interrupts REG 0-ORB/IRB
OUTPUT REGISTER "A" IORA) OR INPUT REGISTER
ODRA=~`~" IOuTPuTt (Input lalching disabled) OfJRB="l" (OUTPUT) MPU writer Output oo~~z*`, 8' f0uTpuT) (Input latching enabled) ORB but no effect ODRA=`*~' ~INPUTI (Input latchlw disabledl On Pin Level untll DORA="O" (INPUT) llnput latching enabledl MPU writes into ORA. but no effect on pin level. until DORA changed MPU writes Output Level IORA)
MPU reads level on PA pl". MPU rea& IRA bit which is the ievel of the PA pin at the time of the last CA1 active transition. MPU reads level on PA Pin. MPU reads IRA bit which is the level of the PA pin at the time of the last CA1 actiue transition
Figure 9. Output Register B (ORB) Input Register B (IRBI
Figure 10. Output Register A (C)RA), Input Register A (IRAI
REG 2 (DDRB) AND REG 3 (DDRA)
PBOIPAO PBl/PAl PB2iPA2
1
"0" ASSOCIATED PB/PA PIN IS AN INPUT (HIGH-IMPEDANCE) "1" ASSOCIATED PB/PA PIN IS AN OUTPUT WHOSE LEVEL IS DETERMINED BY
Figure 11. Data Direction Registers (DDRB, DDRA) Write Handshake The sequence of operations which allows handshaking data from the System processor to a peripheral device is very similar to that described for Read Handshaking. However, for Write Handshaking, the UM6522/A generates the "Data
5-26
UM6522/A
Ready" Signal and the peripheral device must respond with the "Data Taken" Signal. This tan be accomplished on both the PA port and the PB port on the UM6522/A. CA2 or CB2 act as a "Data Ready" output in either the handshake mode or pulse mode and CA1 or CB1 accept the "Data Taken" Signal from the peripheral device, setting the interrupt flag and Clearing the "Data Ready" output. This sequence is shown in Figure 13. Selection of operatrng modes for CAI, CA2, CB1 , and CB2 is accomplished by the Peripheral Control Register (Figure 14).
D A T A R E A D Y [CAl) IRQ OUTPUT READ IRA OPERATION "DATA TAKEN" HANDSHAKE MODE ICA2) "DATA TAKEN" PULSE MODE I l
(CA21
Figure 12. Read Handshake Timing (Port A, Only)
WRITE ORA. ORB OPERATION "DATA READY" HANDSHAKE MODE lCA2. CB21 "DATA READY" PULSE MODE ICA2, CB21 "DATA TAKEN" (CAl. CBl) IRQ OUTPUT 1 I 1 1
I
Figure 13. Write Handshake Timing REG 12 - PERIPHERAL CONTROL REGISTER
CB2 CONTROL 7 16 15 1 OPERATION 0 IO IO ( INmyc~NE>AT!VE. ACTIVE EDGE 0 I 0 I i I INOEPENDENT INTERRUPT INPUT NcG EDGE 0 1 0 INPUT POSITIVE ACTIVE EDGE 011 INDEPENDENT INTERRUPT INPUT POS EDGE 1 0 0 HANDSHAKE OUTPUT 1 0 1 PULSE OUTPUT 1 1 0 LOW OUTPUT 1 1 1 HIGH OUTPUT CB1 INTERRUPT CONTROL-
CA1 INTERRUPT CONTROL 0 = NEGATIVE ACTIVE EDGE 1 = POSITIVE ACTIVE EDGE CA2 CONTROL
-~
0 = NEGATIVE ACTIVE EDGE 1 = POSITIVE ACTIVE EDGE (SEE NOTE ACCOMPANYING FIGURE 251
Figure 14. CAI, CA2, CBI, CB2 Control Timer Operation Interval Timer, Tl, consists of two X-Bit latches and a 16-bit decrement at the $2 clock rate. Upon reaching "zero", an interrupt flag will be set, and IRQ will go low if the interrupt decrements at the 42 clock rate. Upon reaching "Zero" an interrupt flag will be set, and IRQ will go low if the interrupt is enabled. The timer will then disable any further interrupts, or (when programmed to) will automatically transfer the contents of the latches into the counter and begin to decrement again. In addition, the timer may be programmed to invert the output Signal on a peripheral
5-27
GD
UMC
UM6522/A
Two bits are provided in the Auxiliary Control Register (bits 6 and 7) to allow selection of the Tl operating modes. The four possible modes are depicted in Figure 17.
pin each time it "firnes-out." Esch of these modes is discussed separately below. The Tl counter is depicted in Figure 15 and the latches in Figure 16 Reg 4 - Timer 1 Low-Order Counter
Reg 5 - Timer 1 High-Order Counter
COUNT VALUE
WRITE -8 BITS ARE LOA&l I N T O T l L O W - O R D E R L A T C H E S . CATCH C O N T E N T S A R E T R A N S F E R R E D I N T O L O W O R D E R C O U N T E R A T T H E TIME T H E H I G H O R D E R C O U N T E R IS LOADED (REG. 51. READ - 8 B I T S F R O M T l L O W - O R D E R C O U N T E R ARE T R A N S FERRED TO MPU. IN ADDITION. Tl INTERRUPT FLAG IS RESET (BIT 6 IN INTERRUPT FLAG REGISTER).
WRITE -6 BITS LOADED INTO ;, HIGt%ORDER LATCHES. ALSO, AT THIS TIME BOTH HIGH AND LOW-ORDER LATCHES ARE TRANSFERRED INTO THE Tl COUNTER. AND INITIATES COUNTDOWN Tl INTERRUPT FLAG IS A L S O RESET READ - 8 BITS FROM Tl HIGH-ORDER COUNTER TRANSFERRED TO MPU.
Figure 15. Tl Counter Registers Reg 6 - Timer 1 Low-Order Latches
1 2 4
Reg 7 - Timer 1 High-Order Latches
8
1
l-
16
COUNT VALUE
COUNT VALLJE
WRITE-6 B I T S A R E L O A D E D I N T O T l L O W - O R D E R L A T C H E S T H I S O P E R A T I O N IS N O D I F F E R E N T FOLLOWING A WRITE INTO REG 4 R E A D - 6 BITS FAOM Tl LOW-OADER L A T C H E S T R A N S F E R R E D T O MPU. UNLIKE AEG 4 OPERATION, THIS D O E S N C T CAUSE RESET OF Tl INTERRUPT F LAG.
WRITE-6 BITS LOADED INTO Tl HIGH-ORDER LATCHES. UNLIKE REG. 4 OPERATION. NO LATCH-TO-COUNTER TRANS FERS TAKE PLACE. READ- 6 BITS FROM Tl HIGH-ORDER LATCHES ARE TRANSFERRED TO MPU
Figure 16. Tl Latch Registers
Reg 11 - Auxiliary Control Register
Figure 17. Auxiliary Control Register
Note. The processor does not wfite directly to the Iow order counter (TlC-L). Instead. this half of the counter is loaded automatically from the low Order latch when the processor writes to the high Order counter In fact, it may not be necessary to write to the low Order counter in some applications since the timing Operation is triggered by writing to the high Order counter.
5-28
UM6522/A
42 JlJ-1
WRITE T I C - H OPERATION " 00;;;;; (Tl, ONLY) Tl COUNT TZ COUNT I
Figure 18. Timer 1 and Timer 2 One-Shot Mode Timing Timer 1 One-Shot Mode The interval timer one-shot mode allows generation of a Single interrupt for each Timer load Operation. In addition, Timer 1 tan be programmed to produce a Single negative pulse on PB7. To generate a Single interrupt ACR bits 6 and 7 must be "O", then either TI L-L or TIC-L must be written with the low-Order count value. (A write to TIC-L is effectlvely a Write to TIL-L). Next, the high-order count value is written to TIC-H, (the value is simultaneously written into TIL-Hl, and TIL-L is transferred to TIC-L. Countdown begins on 42 following the write TIC-H and decrements at the 92 rate. Tl interrupt occurs when the counters resch "0". Generation of a negative pulse on PB7 is done in the same manner, except ACR bit 7 must be a one. PB7 will go low after a Write TIC-H and go high again when the counters resch "0". The Tl interrupt flag is res.% by either writing TIC-H fstarting a new count) or by reading TIC-L. Timing for the one-shot mode is illustrated in Figure 18. Timer 1 Free-Run Mode The most important advantage associated with the latches in Tl is the ability to produce a continuous series of evenly spaced interrupts and the ability to produce a Square wave on PB7 whose frequency is not affected by variations in the processor interrupt response time. This is accomplished in the "free-running" mode. In the free-running mode, the interrupt flag is set and the Signal on PB7 is inverted each time the counter reaches Zero. However, instead of continuing to decrement from zero after a time-out, the timer automatically transfers the contents of the latch into the counter (16 bits) and continues to decrement from there. lt is not necessary to rewrite the timer to enable setting the interrupt flag on the next time-out. The interrupt flag tan be cleared by reading TIC-L, by writing directly into the flag as will be described later, or if a new count value is desired by a write to TIC-H. All interval timers in the UM6522/A are "re-triggerable". Aewriting the counter will always re-initialize the time-out period. In fact, the time-out tan be prevented completely if the processor continues to rewrite the timer before it reaches Zero. Timer 1 will operate in this manner if the processor w r i t e s i n t o t h e h i g h Order counter (TlC-Hl. However, by loading the latches only, the processor tan access the timer during each down-counting Operation without affecting the time-out in process. I nstead, the data loaded into the latches will determine the length of' the next time-out period. This capability is particularly valuable in the free-running mode with the output enabled. In this mode, the Signal on PB7 is inverted and the interrupt flag is set with each time-out. By responding to the interr u p t s w i t h new data for the latches, the processor tan I determine the period of the next half cycle during each half cycle of the output Signal an PB7. In this manner, very complex waveforms tan be generated. Timing for the free-running mode is shown in Figure 19.
PB7 OUTPUT
Figure 19. Timer 1 Free-Run Mode Timing
'
Note. A precaution to take when using PB7 as the timer output concerns the data direction Register contents for PB7. 60th DDRB bit 7 and ACR bit 7 must be "1" for PB7 to function as the timer output. If either is a "0". then PB7 functions as a normal output pin, controlled by ORB bit 7.
5-29
4!D
UMC
UM6522/A
similar to Timer 1. In this mode, T2 provides a Single interrupt for each "write T2C- H" operatron. After timing out, (reading 0) the counters "roll-over" to all 1's (FFFF,,) and continue decrementing, allowing the user to read them and determine how lang T2 interrupt has been set. However, setting of the interrupt flag will be disabled after initial time-out so that it will not be set by the counter continuing to decrement through Zero. The processor must rewrite T2C-H to enable setting of the interrupt flag. The interrupt flag is cleared by reading T2C-L or by writing T2CH. Timing for this Operation is shown in Figure 18. Reg 9 - Timer 2 High-Order Counter
Timer 2 Operation Timer 2 operates as an interval timer (in the "oneshot" mode only), or as a counter for counting negative pulses on the PB6 peripheral pin. A Single control bit is provided in the Auxiliary Control Regkter to select between these two modes. This timer is comprised of a "write-only" low-Order latch (T2L- L), a "read-only" low-Order counter and a read/write high Order counter. The counter registers act as a 16-bit counter which decrements at the $2 rate. Figure 20 illustrates the T2 Counter Registers. Timer 2 One-Shot Mode As an interval timer, T2 operates in the "one-shot" mode Reg 8 - Timer 2 Low-Order Counter
1 2 4 8 16 32 64 128
COLJNT VALUE
- C O U N T VALUE
1 WRITE - 8 BITS LOADED INTO T2 HIGH-ORDER COUNTER. ALSO, LOW-ORDER LATCHES TRANSFERRED TO LOW-ORDER COUNTER. IN ADDITION, T2 INTERRUPT FLAG IS RESET. R E A D - 8 BITS FROM T2 HIGH-ORDER COUNTER TRANSFERAED TO MPU.
WRITE - 8 BITS LOADED INTO T2 LOW-ORDER LATCHES.
READ -8 BITS FROM T2 LOW-ORDER COUNTER TRANSFERRED TO MPU. T2 INTERRUPT FLAG IS RESET.
Figure 20. T2 bunter Registers Timer 2 Pulse Counting Mode In the pulse counting mode, T2 serves primarily to count a predetermined number of negative-going pulses on PB6. This is accomplished by first loading a number into T2. Writing into T2CH clears the interrupt flag and allows the counter to decrement each time a pulse is applied to PB6. The interrupt flag will be set when T2 reaches Zero. At this time, the counter will continue to decrement with each pulse on PB6. However, it is necessary to rewrite T2C-H to allow the interrupt flag to be set on subsequent downcounting operations. Timing for this mode is shown in Figure 21. The pulse must be low on the leading edge of operating modes are located in the Auxiliary Control Register. Figure 22 illustrates the configuration of the SR data bitsand the SR control bits of the ACR. Figures and 24 illustrate the Operation of the various shift register modes. Interrupt Opetatlon Controlling interrupts within the UM6522/A involves three principal operations. These are flagging the interrupts, enabling interrupts and signaling to the processor that an active interrupt exists within the Chip. Interrupt flags are set by interrupting conditions which exist within the chip or on inputs to the Chip. These flags normally remain set until the interrupt has been serviced. To determine the source of an interrupt, the microprocessor must examine these flags in Order from highest to lowest priority. This is accomplished by reading the flag register into the processor accumulator, shifting this register either right or left and then using conditional branch instructions to detect an active interrupt.
42.
Shift Register Operation The Shift Register (SR) performs serial data transfer into and out of the CB2 pin under control of an internal modulo-8 counter. Shift pulses tan be applied to the CB1 pin from an external Source or, with the proper mode selection, shift pulses generated internally will appear on the CB1 pin for controlling external devices. The control bits which select the various shift register
5-30
UMC
Associated with each interrupt flag is an interrupt enable bit. This tan be set or cleared by the processor to enable interrupting the processor from the corresponding interrupt flag. If an interrupt flag is set to a logic "1" byan interrupting condition, and the corresponding interrupt enable bit is set to a "l", the Interrupt Request Output (m) will go low. IRQ is an "open-collector" o u t p u t which tan b e wire-ORed to other devices in the System to interrupt the
WRITE TZC-H OPERATION PE6 INPUT ~ IRQ OUTPUT N I N-l
UMSSZZ/A
processor. In the UM6522/A, all the interrupt flags are contained in one register. In addition, bit 7 of this register will be read as a logic "1" when an interrupt exists within the Chip. This allows very convenient polling of several devices within a System to locate the Source of an interrupt.
I
N-2
l{ IO
Figure 21. Timer 2 Pulse Counting Mode Reg 10 - Shift Register
Reg IO - H
Reg 11 - Auxiliary Cuntrol Register
SHIFT REGISTER MODE CONTROL SHIFT REGISTER BITS
NOTES: 1. WHEN SHIFTING OUT. BIT 7 IS THE FIRST BIT OUT AND SIMULTANEOUSLY IS ROTATED BACK BIT 0 AND SHIFTED TOWARDS BIT 7. 2. WHEN SHIFTING IN. BITS INITIALLY ENTER BIT 0 AND ARE SHIFTED TOWARDS BIT 7. SHIFT OUT UNOER C
Figure 22. SR and ACR Control Bits . SR Disabled (000) The 000 mode is used to disable the Shift Register. In this mode the microprocessor tan wrlte or read the SR, but the shifting operating is disabled and Operation of CB1 and CB2 is controlled by the appropriate bits in the Peripheral Control Register (PCR). In this mode the SR Interrupt Flag is disabled (held to a logic "0"). Shift in Under Cuntrol of T2 (001) In the 001 mode the shifting rate is controlled by the low Order 8 bits of "T2". Shift Pulses are generated on the CB1 Pin to control shifting in external devices. The time between transitions of this output clock is a function of the System clock period and the contents of the low Order T2 latch (N). The shifting Operation is triggered by writing or reading the shift register. Data is shifted first into the low Order bit of SR and is then shifted into the next higher Order bit of the shift register on the negative-going edge of each clock pulse. The input data should Change before the positive-going edge of the CB1 clock pulse. This data is shifted into the shift register during the 42 clock cycle following the positive-going edge of the CB1 clock pulse. After 8 CB1 clock pulses, the shift register interrupt flag will be set and IRQ will go low.
WRITE OR READ SHIFT REG. CB1 OUTPUT SHIFT CLOCK CB2 INPUT DATA
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UMSSZZ/A
writing the Shift Register. Data is shifted first into bit 0 and is then shifted into the next higher Order bit of the shift register on the trailing edge of each 42 clock pulse. After 8 clock pulses, the shift register interrupt flag will be set, and the output clock pulses on CB1 will stop.
Shift in Under Control of $2 (010) In mode 010 the shift rate is a direct function of the System clock frequency. CB1 becomes an output which generates shift pulses for controlling external devices. Timer 2 operates as an independent interval timer and has no effect on SR. The shifting Operation is trlggered by reading or
REAO SR OPERATION CB1 OUTPUT SHIFT CLOCK CB2 INPUT DATA
Figure 23-2 Shift Register Input Modes Shift in Under C o n t r o l o f E x t e r n a t CB1 Glock (Oll) In mode Oll CB1 becomes an input. This allows an external device to load the shift register at its own Pace. The shift register counter will interrupt the processor each time 8 bits have been shifted in. However, the shift register counter does not stop the shifting Operation; it acts simply as a pulse counter. Reading or writing the Shift Register resets the Interrupt flag and initializes the SR counter to count another 8 pulses. Note that the data is shifted durrng the first System clock cycle following the positive-going edge of the CB1 shift pulse. For this reason, data must be held stable during the first full cycle after CB1 goes high.
CB1 OUTPUT SHIFT CLOCK
Figure 23-3 Shift Register Input Modes
Shift Out Free-Running at T2 Rate (1001 Mode 100 is very similar to mode 101 in which the shift rate is set by T2. However, in mode 100 the SR Counter does not stop the shift Operation. Since Shift Register bit 7 (SR7) is circulated back into bit 0, the 8 bits loaded into the shift register will be clocked onto CR2 repeatedly. In this mode the shift register counter is disabled, and IRQ is never Set.
WRITE SR OPERATION CB1 OUTPUT SHIFT CLOCK CB2 INPUT DATA
Figure 24-1 Shift Register Output Modes
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GD
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UMSSZZ/A
generated on CB1 to control shifting in external devices. After the 8 shift pulses, shifting is disabled, the SR Interrupt Flag is set and CB2 remains at the last data level.
Shift Out Under Control of T2 (1011 In mode 101 the shift rate is controlled by TZ (as in the However, with each read or write of previous model. the shift register the SR Counter is reset and 8 bits are shifted onto CB2. At the same time, 8 shift pulses are
$2 CLOCK WRITE SR OPERATION CB1 OUTPUT SHIFT CLOCK CB2 INPUT DATA IRQ
Figure 24-2 Shift Register Output Modes Shift Out Under Control of 9 2 (1 IO) In mode 110, the shift rate is controlled by the $2 System clock.
WRITE SR OPERATION CB1 OUTPUT SHIFT CLOCK CB2 INPUT DATA IRQ
Figure 24-3 Shift Register Output Modes Shift Out Under Control of External CB1 Glock (111) In mode 111, shifting is controlled by pulses applied to the CB1 pin by an external device. The SR counter sets the SR Interrupt flag each time it counts 8 pulses but it does not disable the shrfting function. Esch time the microorocesor writes or reads the shift register, the SR Interrupt flag is reset and the SR counter is initialized to begin counting the next 8 shift pulses on pin GBl. After 8 shift pulses, the interrupt flag is set. The microprocessor tan then load the shift register with the next byte of data.
dJ2 WRITE SR OPERATION _
SHIFT CLOCK CB2 OUTPUT IRQ
Figure 24-4 Shift Register Output Modes
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tan Set or clear selected bits in this register to facilitate controlling individual interrupts without affecting others. This is accomplished by writing to address 1110 (IER address). If bit 7 of the data placed on the System data bus during this write Operation is a "O", each "1 " in bits 6 through 0 clears the corresponding bit in the Interrupt Enable Register. For each "zero" in bits 6 through 0, the corresponding bit is unaffected. Setting selected bits in the Interrupt Enable Register is accomplished by writing to the same address with bit 7 in the data word set to a logic "1". In this case, each "1" in bits 6 through 0 will set the corresponding bit. For each "Zero", the corresponding bit will be unaffected. The individual control of the setting and Clearing operations allows very convenient control of the interrupts during System Operation. In addition to setting and Clearing IER bits, the processor tan read the contents of this register by placing the proper address on the register select and chip select inputs with the Rmline high. Bit 7 will be read as a logic "1 "
The Interrupt Flag Register (IFR) and Interrupt Enable Register (IERI are depicted in Figures 25 and 26, respectively. The IFR may be read directly by the processor. In addition, individual flag bits may be cleared by writing a "1" into the appropriate bit of the IFR. When the proper chip select and register Signals are applied to the Chip, the contents of this register are placrxf on the data bus. Bit 7 indicates the Status of the IRQ output. This bit corresponds to the logic function. IRQ = IFR6 x IER6 + IFR5 x IER5 + IFR4 x IER4 + IFR3 x IER3 + IFR2 x IER2 + IFRl x IERl + IFRO x IERO. Note: X = l o g i c AND, += Logic OR. T h e IFR bit 7 is not a flag. Therefore, this bit is not directly cleared by writing a logic "1" into it, lt tan only be cleared by Clearing all the flags in the register or by disabling all the active interrupts as discussed in the next section. For each interrupt flag in IFR, there is a corresponding bit in the Interrupt Enable Register. The System processor
Reg 13 - Interrupt Flag Register
Reg 14 - Interrupt Enable Register
SET BY
CLEAAEO BY CA1
. IF THE CA2KB2 CONTROL IN THE PCR IS S E L E C T E D A S "INDEPENDENT" INTERRUPT INPUT, THEN READING OR W R I T I N G T H E O U T P U T R E G I S T E R ORA/ORB W I L L N O T C L E A A T H E F L A G B I T . INSTEAD. T H E B I T M U S T B E C L E A A E D B Y W R I T I N G I N T O T H E IFR. AS DESCRIBED PREVIOUSLY,
Notes: 1 . I F B I T 7 ISA"O",THEN EACH"1"INBlT.S0.6DISABLESTHE CORRESPONDING INTERRUPT. 2. IF BIT 7 IS A "l",THEN EACH "1" IN BITSO-6 E N A B L E S T H E COARESPONDING INTERRUPT. 3. IF A READ OF THIS REGISTER IS DONE, BIT 7 WILL BE "1" A N D A L L O T H E R B I T S W I L L R E F L E C T THEIR ENABLEI DISABLE STATE.
Figure 25. Interrupt Flag Register (IFRI
Figure 26. Interrupt Enable Register (IER)
Ordering Information
Part Number UM6522 UM6522A Frequency 1 MHz 2 MHz Package 40L DIP 40L DIP
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